Plated Gold Pogo Probe

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Plated Gold Pogo Probe

Given the different physical nature of the structure, you’ll see different failure modes. But by and large, the test is abstracted from the individual transistors, so I don’t know that you’re going to see a big difference. Anytime the industry goes through one of these major architectural changes you typically do see a bump up in test intensity. They’ve got to figure out what the failure modes associated with this new transistor structure are, and the overall physical architecture. We saw some of that at the first finFET nodes, whether that was 22nm in the microprocessor space or 14/16nm in the foundry space.

Plated Gold Pogo Probe

A good example of that is power delivery and/or power impedance specs in the probe card. If you’re trying to deliver all this power into the chip from the test instrumentation, the path through which you do that becomes a lot more important and the specs need to be a lot tighter. Five years ago the power delivery performance of the probe card wasn’t that big a deal. Now it is a major design consideration, and it’s one of the reasons why we end up working so closely with fabless customers. They understand the different tolerances and specifications that each of those power supplies will have. Some are a little bit looser, some need to be extremely tight. As you design the probe card specific to each design, that becomes one of the major performance concerns.

Plated Gold Pogo Probe

Almost all of what we do is either bare die or full wafer, so the package ends up being a downstream piece of this. But you do see a lot of the same implications associated with the power delivery ending up being constraints in the package design. Historically, packaged substrates were pretty simple structures — a couple of layers of metal, not a lot of really stringent design requirements. That’s changed. Now we’re seeing much more complicated packaging substrates with more layers. Via densities are going way up. You need to manage and tailor the power supply performance. This is becoming a big deal — not just for testing at the wafer level with a probe card, but also in the final package.

Plated Gold Pogo Probe

You’re testing to make sure that each of these component die is functionally good, or good enough to be repaired in the final package. And because they’re being fabricated on fairly advanced nodes — at least 1x or 1y nanometer DRAM nodes, the yields are not great. And so it’s a simple functional characterization of making sure that the die that goes into the stack is as close to good as they can get. I’m reluctant to use the term ‘known good die’ because it conveys the notion of a perfect thing, and nothing in the semiconductor industry is perfect. There’s a balance of cost versus the risk that people constantly play with, and for DRAM there is some level of repairability and redundancy. So you see all of those different knobs being exercised. But HBM for sure has impacted not just the volumes of our DRAM probe card business, but also the spec requirements as they continue to tighten them up.

For the reliability aspect of some of these newer devices, people are still figuring this out. But there are things analogous to burn-in and accelerated testing, either through temperature or vibration testing. They are figuring out different ways to accelerate the most likely failure modes in the field or things that people are concerned about. I’ve had conversations with several customers, but at this point backing up the full functional tests for these devices, both electrical and optical, is where we are focused on this point.

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